1. Field of the Invention
The present invention relates to a semiconductor memory device having an ultrahigh density of integration above 1 gigabit, and more particularly to a semiconductor memory device using an epitaxial planar capacitor possessing a dielectric thin film made of dielectric material having a perovskite-type structure or another crystal structure.
2. Description of the Related Art
Recently, memory devices (FRAM: Ferroelectric Random Access Memory) using ferroelectric thin films for storage capacitors are developed and some of them have practical application. Ferroelectric random access memory (FRAM) is a nonvolatile memory and has a feature that the contents of memory are not lost even after cutting off the electric power supply. Furthermore, it has a feature that high speed accessing as fast as DRAM are possible, owing to fast reversion of the spontaneous polarization, if the ferroelectric film is sufficiently thin. FRAM is also suitable to growing up of the capacitance because one unit memory cell can be formed by one switching transistor (1-T) and one ferroelectric capacitor.
A ferroelectric thin film suitable to a ferroelectric memory is required to have a large remnant polarization and low temperature dependence thereof and to be capable of retention of the remnant polarization for a long time. Lead zirconate titanate (PZT) is now mainly used as a ferroelectric material. PZT is a solid solution of lead zirconate (PbZrO.sub.3) and lead titanate (PbTiO.sub.3) in which mole fraction of near 1:1 is considered to produce good memory medium owing to large spontaneous polarization and possibility of reversion even at low electric field. PZT has a relatively high transition temperature between ferroelectric and paraelectric phases(Curie temperature) of above 300.degree. C. and so it is rare to lose the memorized information by heat in the temperature range in which the conventional electronic circuits are used.
However, it is known that formation of high quality thin films of PZT is difficult. The reason is, first, accurate control of the stoichiometric composition is difficult because lead which is a main component of PZT is vaporized above 500.degree. C. and second, though the ferroelectricity appears when PZT forms a perovskite-type structure, the structure called "pyrochlore" is more easily obtained than perovskite structure. In addition, preventing diffusion of the main component, lead, into silicon is difficult when a PZT thin film is applied to a silicon device.
Besides PZT, barium titanate (BaTiO.sub.3) is known to be a representative ferroelectric substance. It is known that similarly to PZT, barium titanate has a perovskite-type structure the Curie temperature of which is about 120.degree. C. Control of the stoichiometric composition is relatively easy in the formation of barium titanate thin films because Ba is harder to vaporize than Pb. Further, barium titanate rarely crystallizes into a crystal structure other than perovskite-type structure. In spite of these advantages, epitaxial planar capacitor of barium titanate is not so much investigated as a storage capacitor for ferroelectric memory device. The reason is the weak remnant polarization and the large temperature dependence thereof, compared with PZT. A cause of these facts is the low Curie temperature (120.degree. C.) of barium titanate resulting in the possibility of losing the memory contents when the ferroelectric memory is exposed to high temperatures above 100.degree. C. Additionally, barium titanate shows large temperature dependence of the remnant polarization even in the temperature range (below 85.degree. C.) usually used for electronic circuits, resulting in an unstable operation. Hence, the epitaxial planar capacitor using ferroelectric thin film composed of barium titanate is usually considered to be unsuitable to use for the memory medium of a ferroelectric memory device.
In order to solve the above-mentioned problems, the present inventors studied the structure of epitaxial planar capacitors and investigated various materials. And as a result the present inventors selected a single crystal substrate such as strontium titanate (STO) or magnesium oxide (MgO), a bottom electrode such as strontium ruthenate (SrRuO.sub.3, hereafter denote simply as SRO), and a dielectric material (for example, barium strontium titanate, Ba.sub.x Sr.sub.1-x TiO.sub.3, hereafter denoted simply as BST) having a lattice constant near and a little larger than that of (100) plane of the bottom electrode layer, as a ferroelectric thin film used for an epitaxial planar capacitor. Then BST was grown epitaxially in the direction of c-axis which is a polarization axis, using a RF magnetron sputtering method. Misfit dislocations are relatively hard to be generated in the growing process of thin films by the RF magnetron sputtering method. As a result, it was found that even in the dielectric thin film having relatively large film thickness above 200 nm, the lattice constant can be retained in such a state as elongating in the direction of thickness (c-axis direction) and shrinking in the direction of lattice plane (a-axis direction) relative to an original one. Consequently, it was ascertained by the present inventors that a ferroelectric thin film such that the Curie temperature is shifted to higher temperature, remnant polarization near room temperature is large and sufficiently large remnant polarization can be kept at temperatures up to about 85.degree. C. is realizable. For example, it was ascertained experimentally that desirable ferroelectric properties in practical application are realizable by using for example, a conductive perovskite crystal, SRO, (lattice constant a=0.393 nm) as the bottom electrode layer of epitaxial planar capacitor and using Ba.sub.x Sr.sub.1-x TiO.sub.3 in the compositional region of x=0.30-0.90 as a dielectric substance, owing to an appearance of ferroelectricity even in a compositional region (x.ltoreq.0.7) in which the ferroelectricity is not usually expected to appear at room temperature and further owing to further increase of the Curie temperature which is originally above room temperature, in the compositional region showing ferroelectricity (x&gt;0.7) at room temperature. In the same way, it was ascertained by the present inventors that a capacitor having a large dielectric constant reaching to for example, more than 800 and a film thickness of 20 nm, by using a conductive perovskite crystal, SRO, as a bottom electrode layer and Ba.sub.x Sr.sub.1-x TiO.sub.3 in the compositional region x=0.10-0.40 as a dielectric substance. The dielectric constant is several times larger than the value of about 200 in the capacitor with the same film thickness made by polycrystalline film. Such a large dielectric constant is very desirable on the formation of DRAM.
In any case, a three-dimensional bonded structure, wherein a miniaturized transistor and a capacitor capable of offering a fixed capacitance even with a small area are three-dimensionally bonded, is essential for accomplishing a semiconductor memory device with ultrahigh integration density of over 1 gigabit. As already explained, an epitaxial planar capacitor is promising as a capacitor capable of offering a required capacitance even with a small area. A structure wherein a switching transistor, formed on a semiconductor substrate, is bonded with an epitaxial planar capacitor, deposited on an oxide substrate such as magnesium oxide (MgO) or strontium titanate(STO) is known as a method of three-dimensionally stacking a switching transistor and an epitaxial planar capacitor. For instance, Japanese Patent Laid-Open Application Publication No. 8-139292 (see FIG. 19G of this publication) and Japanese Patent Laid-Open Publication No. 8-227980 (see FIGS. 1 and 2) disclosed a structure for a semiconductor device wherein a semiconductor substrate was bonded to an oxide substrate such as MgO or STO. By growing on the oxide substrate, the conventional semiconductor memory device using the oxide substrate utilized stress, caused by mismatch between the lattice constants of the oxide substrate and the dielectric thin film, to shift the ferroelectric Curie temperature toward the high temperature side, thereby obtaining ferroelectric properties at room temperature. In other words, an oxide substrate was essential in order to artificially control the c axis length of BSTO, with BSTO as warped lattice using "epitaxial effect".
However, this phenomenon lead to the following disadvantages of the semiconductor memory device using an oxide substrate:
(1) Although a silicon wafer (semiconductor substrate) with a diameter greater than 8 inches can easily be obtained commercially, it is extremely difficult to obtain an oxide substrate, such as an MgO substrate or an STO substrate, with a diameter greater than 3 inches even at the research level. If a wafer with a diameter less than 3 inches is used as a base substrate, mass production of the semiconductor will be difficult. Therefore, a semiconductor memory device using an oxide substrate has a high production cost per chip.
(2) A semiconductor substrate has a thermal expansion coefficient of 2.5 ppm/.degree. C., but an MgO substrate and an STO substrate have a thermal expansion coefficient of 9 ppm/.degree. C. Therefore, after bonding at for instance 500.degree. C., the oxide substrate would suffer a tensile stress of greater than several kg/mm.sup.2 when cooled to room temperature and would consequently split. Even when the oxide substrate did not actually split, very considerable bending would be caused. Since semiconductor memory devices of the gigabit generation require ultrafine processing at the submicrometer to nanometer levels, when bending of the substrate occurs, subsequent lithography becomes impossible.
Furthermore, in addition to these inherent disadvantages when using an oxide substrate, the semiconductor memory device disclosed in Japanese Patent Laid-Open Publication Nos. 8-139292 and 8-227980 have the following disadvantages:
(3) The surface of the semiconductor substrate comprises a metal electrode layer portion (first bonding layer) and an insulating portion. Similarly, the surface of the oxide substrate which faces the semiconductor substrate comprises a metal electrode layer portion (second bonding layer) and an insulating portion. Conditions for connecting metal electrode layer portions are generally different from conditions for connecting insulating portions. Therefore, it is difficult to evenly stick the two substrates under same bonding conditions for these metal electrode layer portions and insulating portions.
(4) The pattern of the electrode layer portion (source region) of a switching transistor formed on the semiconductor substrate and the pattern of the electrode layer portion (first electrode layer, upper first barrier metal layer) of a capacitor formed on the oxide substrate must be aligned and connected in a one-to-one arrangement. However, as described above, it is virtually impossible to match patterns, which have been formed on substrates having different thermal expansion coefficients, with submicrometer precision over the entire wafer surfaces at high temperature.
On the other hand, use of a dielectric planar capacitor grown epitaxially for semiconductor memory such as FRAM and DRAM or another device is attempted and examined. A typical known example is a method as follows: on a semiconductor substrate wherein a switching transistor is formed previously, an opening portion (contact hole) is formed on the electrode layer of a switching transistor through an interlayer insulating film covering the switching transistor and a single crystalline silicon plug is formed in the contact hole by selective epitaxial growth from vapor phase or solid phase epitaxial growth from amorphous state and an epitaxial planar capacitor is formed thereon (U.S. Pat. No. 5,739,563) (hereafter denoted "a first technique"). It is capable of forming a stacked epitaxial planar capacitor just above an electrode layer of a switching transistor by this method. Hence, it can be said that this structure is basically one of the most suitable structures to high density integration.
As another fabrication method, the method using SOI substrate is proposed. This is such a method(hereafter denote "a second technique") that a second semiconductor substrate is stuck on a first semiconductor substrate whereon an epitaxial planar capacitor is formed previously and a thin film is made by polishing. And a contact plug for connecting an electrode layer of a capacitor on a first silicon plug to an electrode layer on a second semiconductor substrate is formed. Further, a switching transistor is formed on a second semiconductor substrate. In this second technique, the formation is easy as an epitaxial planar capacitor and a switching transistor are formed on separate substrates and the structure is suitable to high density integration as a switching transistor can be stacked just upon an epitaxial planar capacitor.
Semiconductor memory devices for gigabit levels are now becoming important. However, in a semiconductor memory device with high density of integration of 4, 16 or 64 gigabits, an aspect ratio of depth to width of the contact hole formed in the insulating film on the electrode layer of a switching transistor is necessarily becoming large. On the above-mentioned first technique, a process window for selective epitaxial growth, or solid phase epitaxial growth of a single crystal silicon plug only from the bottom surface of a contact hole with large aspect ratio becomes narrow, and consequently, yield of fabricating more than tens of millions of plugs in a memory device is low and it is difficult to apply to a mass production line.
According to the above-mentioned second technique, it is necessary to make interconnection between the capacitor and the switching transistor through bonding interface. Hence, perfect bonding is required in order to avoid formation of voids at the bonding interface which leads to faulty products. In addition, there is a problem of difficulty in precisely fitting and aligning the positions of capacitor and switching transistor owing to their separate formation processes.
As above-mentioned, there are many technical problems to be solved in the first and the second techniques.